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Cadence Design Systems, a global electronic design innovation company, announced that Chinese mobile chipset provider Innofidei, in close collaboration with Cadence Global Services, has successfully taped out the industry's first long-term evolution time division duplex or “LTE (News - Alert)-TDD,” also known as “TD-LTE” baseband chip supporting a bandwidth of 20MHz for the next-generation TD-CDMA wireless communications protocol.
Working with the Innofidei team, Cadence delivered netlist-to-GDSII implementation in a record four months turnaround time, helping Innofidei tighten the productivity gap as outlined in the EDA360 vision, according to company officials.
Cadence Global Services help customers maximize their design team productivity and company profitability. Working as part of the customer’s design team, Cadence Global Services experts ensure that Cadence technology is applied in the most beneficial way to achieve the customer's business goals.
Innofidei provides IC and system solutions for the mobile TV and wireless communication markets. Company officials says Innofidei's 65-nanometer, low-power SoC is integrated into a mobile terminal system successfully tested by China Mobile (News - Alert) Communications Corporation and is being demonstrated at EXPO Shanghai 2010.
“The fast, flexible and comprehensive design capabilities offered by Cadence Global Services minimized our risk and became a vital enabler for the first-time-right completion of this design,” Tom Zhang, chief executive officer at Innofidei, said. “This process was all completed within a very aggressive schedule and with the most challenging design targets.”
According to Veronica Watson, vice president, Asia Pacific Field Operations at Cadence, the design collaboration infrastructure, project management expertise and world-class design expertise of their company helps customers like Innofidei tackle groundbreaking new designs in a shorter time-to-market window so they can narrow the productivity gap and begin targeting the profitability gap.
Recently Cadence announced plans to use open-source reference flow for verification of system-on-chip using Universal Verification Methodology standard, TMCnet reported. With this, engineers will be able to adopt advanced verification techniques where the deployment effort and the risk get minimized and the time-to-market targets can be easily realized.
Source: TMC Net |
