16nm Tera-Scale Memory Project led by Glasgow University
Glasgow University is the key team in an EU funded group who are looking at ways of designing memories which take into account the variability and unreliability of nano-scale transistors at process geometries around 16nm.
Professor Asen Asenov, of the Department of Electronic and Electrical Engineering is leading the Glasgow team in the project which is called 'Tera-scale Reliable Adaptive Memory Systems' (TRAMS).
"Tera-scale computing will transform the power, performance and functionality of personal computers, phones and other electronic devices as well as large computing facilities such as data centres", said Asenov, "however, if we are to continue to shrink the size of transistors in order to develop such powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the variability within transistors."
Asenov's Glasgow team is joined by researchers from Intel, Interuniversitair Micro-Elektronica Centrium vzw and the Universitat Politecnica de Catalunya.
The work is being funded by the EU's Framework Programme 7 (FP7) science research fund.
The problem the group is addressing is that, at very advanced process geometries, around 16nm, variations within transistors' structures affect their performance and thus the reliability of ICs.
"We hope this project will result in new chip design paradigms for building reliable memory systems out of unreliable nano-scale components cheaply and effectively," said Asenov.
Central to the project is simulation software developed by Asenov in an earlier £5.3m Engineering and Physical Sciences Research Council eScience pilot project called NanoCMOS.
The NanoCMOS simulations use grid computing, which utilises the processor power of thousands of linked computers, to simulate how hundreds of thousands of transistors, each with their own individual characteristics, will function within a circuit.
Asenov and the University of Glasgow are setting up a company called Gold Standard Simulations to exploit this technology which will be critical to the work of the TRAMS project, with all device design and simulation work being conducted at Glasgow. The 16nm transistors will be design and simulated exclusively by Glasgow.
The TRAMS consortium will also consider what are known as 'Beyond CMOS' technologies; nanowire transistors, quantum devices, carbon nanotubes and molecular electronics, which are expected to be as small as five nanometres.
The project is expected to last three years.
Previous Story: Cargo carrier of the cells is lifes smallest motor
Next Story: A new approach to optimizing molecular self-organization
The Institute of Nanotechnology puts significant effort into ensuring that the information provided on its news pages is accurate and up-to-date. However, we cannot guarantee absolute accuracy. Consequently, the Institute of Nanotechnology disclaims any and all responsibility for inaccuracy, omission or any kind of deficiency in relation to the news items and articles hosted herein.
- 04 March 2014NanoCelluComp presents final results at JEC Europe 2014
- 17 February 2014Researchers Hijack Cancer Migration Mechanism to “Move” Brain Tumours
- 12 February 2014Fingerprinting meningitis with lasers
- 06 February 2014European Innovation Convention 2014
- 30 January 2014NanoSafety Cluster Newsletter No.2 - Out Now
- View All