Fabrication Technique Could Yield Low-cost Scalable Nanowire

 
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PostPosted: Mon May 11, 2009 3:27 pm    Post subject: Fabrication Technique Could Yield Low-cost Scalable Nanowire Reply with quote

Fabrication Technique Could Yield Low-cost, Scalable Nanowire Photonic and Electronic Circuits

Applied scientists at Harvard University in collaboration with researchers from the German universities of Jena, Gottingen, and Bremen, have developed a new technique for fabricating nanowire photonic and electronic integrated circuits that may one day be suitable for high-volume commercial production.

Spearheaded by graduate student Mariano Zimmler and Federico Capasso, Robert L. Wallace Professor of Applied Physics and Vinton Hayes Senior Research Fellow in Electrical Engineering, both of Harvard's School of Engineering and Applied Sciences (SEAS), and Prof. Carsten Ronning of the University of Jena, the findings will be published in Nano Letters. The researchers have filed for U.S. patents covering their invention.

While semiconductor nanowires - rods with an approximate diameter of one-thousandth the width of a human hair - can easily synthesized in large quantities using inexpensive chemical methods, reliable and controlled strategies for assembling them into functional circuits have posed a major challenge. By incorporating spin-on glass technology, used in Silicon integrated circuits manufacturing, and photolithography, transferring a circuit pattern onto a substrate with light, the team demonstrated a reproducible, high-volume, and low-cost fabrication method for integrating nanowire devices directly onto silicon.


The basic structure of the nanowire devices is based on a sandwich geometry in which a nanowire (n-type zinc oxide) is placed between the substrate (heavily doped p-type silicon) and a top metallic contact, using spin-on glass as an insulating spacer layer to prevent the metal contact from shorting to the substrate (as shown in (a) and (b)). This allows for uniform injection of current along the length of the nanowire. A finished wafer using the team's method is shown in (c), with a typical device shown in (d). Note that a stray nanowire intercepts the device on the upper part of (d). The oval feature surrounding the stray nanowire is due to the varying thickness of the spin-on glass film. When a voltage is applied to this device, it emits ultraviolet light (as shown in image (e) obtained with a CCD camera) with a peak wavelength of ~380 nm.


"Because our fabrication technique is independent of the geometrical arrangement of the nanowires on the substrate, we envision further combining the process with one of the several methods already developed for the controlled placement and alignment of nanowires over large areas," said Capasso. "We believe the marriage of these processes will soon provide the necessary control to enable integrated nanowire photonic circuits in a standard manufacturing setting.

The structure of the team's nanowire devices is based on a sandwich geometry: a nanowire is placed between the highly conductive substrate, which functions as a common bottom contact, and a top metallic contact, using spin-on glass as a spacer layer to prevent the metal contact from shorting to the substrate. As a result current can be uniformly injected along the length of the nanowires. These devices can then function as light-emitting diodes, with the color of light determined by the type of semiconductor nanowire used.

To demonstrate the potential scalability of their technique, the team fabricated hundreds of nanoscale ultraviolet light-emitting diodes by using zinc oxide nanowires on a silicon wafer. More broadly, because nanowires can be made of materials commonly used in electronics and photonics, they hold great promise for integrating efficient light emitters, from ultraviolet to infrared, with silicon technology. The team plans to further refine their novel method with an aim towards electrically contacting nanowires over entire wafers.

"Such an advance could lead to the development of a completely new class of integrated circuits, such as large arrays of ultra-small nanoscale lasers that could be designed as high-density optical interconnects or be used for on-chip chemical sensing," said Ronning.

The team's co-authors are postdoctoral fellow Wei Yi and Venkatesh Narayanamurti, John A. and Elizabeth S. Armstrong Professor and dean, both of Harvard's School of Engineering and Applied Sciences; graduate student Daniel Stichtenoth, University of Gottingen ; and postdoctoral fellow Tobias Voss, University of Bremen .

The research was supported by the National Science Foundation (NSF) and the German Research Foundation. The authors also acknowledge the support of two Harvard-based centers, the National Science Foundation Nanoscale Science and Engineering Center (NSEC) and the Center for Nanoscale Systems (CNS), a member of the National Nanotechnology Infrastructure Network (NNIN).


Source: http://www.seas.harvard.edu/newsandevents/pressreleases/050808_Nano.html
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